Fit to programme

This was a proposed solution answering Task 001, behind WP 1.1.

Summary

The HPC Hardware Lab at Durham University is a leading laboratory for researchers wishing to access the latest cutting edge technologies relevant for HPC. It includes the latest GPU models, CPUs, networking technologies, storage, and extends to data centre infrastructure, including immersion cooling and waste heat reuse. This Lab has grown organically over time, and so much of the documentation has tracked its progress. This means that it is not always straightforward to navigate, nor to find out how to access a particular hardware component (authorisation and authentication), and how to best make use of that hardware. This proposal therefore cleans up the documentation, makes it consistent across various locations, integrates links into the SHAREing testbed database (https://shareing-dri.github.io/tasks/009_portal/) and also ensures that there is consistency with the criteria identified by Task 001 (defining a common description for Hardware Lab components).

Outcomes

The primary output will be a detailed, publicly available report that explains how to identify classical components of an algorithm that are suitable for quantum acceleration, sets out clear criteria for selection, and shows how to reformulate those tasks for quantum execution. It will also address the practical caveats required to achieve genuine end-to-end gains in practice, such as data movement, resource estimates, error budgets, and hybrid integration. Although developed in the context of SWIFT, the core methodology will be transferable to other research codes and valuable to the wider UK community. Subject to securing separate funding (currently pending) for access to quantum systems, this could also potentially produce a publication that quantifies endto-end speedups in SWIFT, extending our earlier work on quantum-assisted load balancing.